Building FAST

Historically, software simulation has been the vehicle of choice for studying computer architecture because of its flexibility and low cost. Regrettably, designers of software simulators must choose between providing high performance or detailed hardware emulation. Building hardware, in contrast, provides high performance and accurate results, but lacks the flexibility to explore multiple designs and is very expensive. These tradeoffs have impeded our ability to thoroughly explore and evaluate new computer architectures.
The Flexible Architecture for Simulation and Testing (FAST) provides a foundation for future many core and TLP-focused computer architecture research by combining the flexibility of software with the accuracy and speed of hardware enabling Computer Architects to implement/simulate new multithreaded, multiprocessor, or Chip Multiprocessor (CMP) architectures for in-depth evaluation and software development. By combining dedicated microprocessor, SRAMs and Field Programmable Gate Arrays (FPGAs), FAST operates at hardware speeds and can emulate on and off chip latency and bandwidth. This book describes the implementation, architecture and proposes the next generation!