SRAM Design in Nanometer Technologies

In the design of VLSI, where an improvement in minimum supply voltage and a change in few Pico seconds of memory access or cycle times will make a big impact on SoC designs performance. SRAM cell write-ability and read stability are of prime concern at low supply voltages and also for process, voltage and temperature variations. When low supply voltage is applied to SRAM cell, the write operation will not be performed because the cell will not flip to desired voltage levels. A write assist circuit using a negative bitline voltage technique which can assist SRAM cell to flip to the desired voltage levels and assists the write operation is proposed for reducing write failures at low supply voltages.When low supply voltage applied to SRAM cell the read operation will not be performed in the selected cell and the cell stored data will be disturbed in the unselected cells. The proposed lowered WL voltage read assist circuit technique prevents the data from getting disturbed in unselected cells and also assists the read operation in selected cell.